Chemical-mechanical polishing (CMP) compositions and methods for polishing (or planarizing) the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries, CMP slurries, and CMP compositions) for polishing metal layers (such as tungsten) on a semiconductor substrate may include abrasive particles suspended in an aqueous solution and chemical accelerators such as oxidizers, chelating agents, catalysts, and the like.
In a conventional CMP operation, the substrate (wafer) to be polished is mounted on a carrier (polishing head) which is in turn mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus (polishing tool). The carrier assembly provides a controllable pressure to the substrate, pressing the substrate against the polishing pad. The substrate and pad are moved relative to one another by an external driving force. The relative motion of the substrate and pad abrades and removes a portion of the material from the surface of the substrate, thereby polishing the substrate. The polishing of the substrate by the relative movement of the pad and the substrate may be further aided by the chemical activity of the polishing composition (e.g., by an oxidizing agent and other chemical compounds present in the CMP composition) and/or the mechanical activity of an abrasive suspended in the polishing composition.
In typical tungsten plug and interconnect processes, tungsten is deposited over a dielectric and within openings formed therein. The excess tungsten over the dielectric layer is then removed during a CMP operation to form tungsten plugs and interconnects within the dielectric. As semiconductor device feature sizes continue to shrink, meeting local and global planarity requirements has become more difficult in CMP operations (e.g., in tungsten CMP operations). Array erosion (also referred to as oxide erosion), plug and line recessing, and tungsten etching defects are known to compromise planarity and overall device integrity. For example, excessive array erosion may lead to difficulties in subsequent lithography steps as well as cause electrical contact problems that can degrade electrical performance. Tungsten etching/corrosion and plug and line recessing may also degrade electrical performance or even cause device failure.
In order to meet the local and global planarity requirements commercial tungsten CMP operations sometimes employ multiple polishing steps. For example, a first step may be employed to remove bulk tungsten metal from the substrate while a second step may be employed to remove any remaining tungsten and various binder layers from the underlying dielectric layer. A second polishing step is sometimes also employed to remove defects from the underlying dielectric layer. While such multi-step polishing operations may improve device planarity, there remains a need in the industry for further improvements, particularly for tungsten CMP slurries (or compositions) that are suitable for use in a second polishing step.